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ED060XC3 is a reflective electrophoretic E Ink® technology display module based on active matrix TFT substrate featuring capacitive touch panel. It has 6” active area with 758 x 1024 pixels, the display is capable to display images at 2-16 gray levels (1-4 bits) depending on the display controller and the associated waveform file it used.

  • High contrast reflective/electrophoretic technology
  • 758 x 1024 dots resolution
  • Capacitive touch
  • High reflectance
  • Ultra wide viewing angle
  • Ultra low power consumption
  • Pure reflective mode
  • Bi-stable
  • Commercial temperature range
  • Landscape, portrait mode
  • Module with capacitive touch panel

 
Parameter Specifications Unit Remark

Screen Size

6.0 (3:4 diagonal)

Inch

Display Resolution

758 (H)×1024(V)

Pixel

Active Area

90.58 (H)×122.37 (V)

mm

Pixel Pitch

0.1195 (H)×0.1195 (V)

mm

Pixel Configuration

Square

Outline Dimension

101.80(W)×138.40(H)×1.58(D) (EPD+Touch)

mm

Module Weight

50±5

g

Number of Gray

16 Gray Level (monochrome)

Display operating mode

Reflective mode

5-1) Connector type: FH34S-34S-0.5SH(50)-Hirose

Pin Assignment

 
Pin # Signal Description Remark

1

VGG

Positive power supply gate driver

2

VPOS

Positive power supply source driver

3

VSS

Ground

4

BORDER

Border connection

5

VDD2

SPI power supply (1.8V)

6

SPV

Start pulse gate driver

7

CKV

Clock gate driver

8

MODE 1

Output mode selection gate driver

9

VSS

Ground

10

SPI_SDO

Serial Data Output for Flash memory

Note5-1

11

SPI_NCS

Chip Select for Flash memory

Note5-1

12

SPI_SDI

Serial Data Input for Flash memory

Note5-1

13

SPI_SCL

Serial Data Clock for Flash memory

Note5-1

14

VCOM

Common connection

15

D7

Data signal source driver

16

D6

Data signal source driver

17

D5

Data signal source driver

18

D4

Data signal source driver

19

D3

Data signal source driver

20

D2

Data signal source driver

21

D1

Data signal source driver

22

D0

Data signal source driver

23

XSTL

Start pulse source driver

24

XOE

Output enable source driver

25

XLE

Latch enable source driver

26

VSS

Ground

27

XCL

Clock source driver

28

VSS

Ground

29

VDD

Digital power supply drivers (3.3V)

30

AGND

Thermistor Analog Ground

Note 5-2

31

TS

Thermistor Sense Pin

Note 5-2

32

VSS

Ground

33

VEE

Negative power supply gate driver

34

VNEG

Negative power supply source driver

Note 5-1

Note 5-2

5-2) Flash Format

6-1) Connector type:8 Pin Pitch=0.5mm(P-TWO196033-08041)

6-2) Pin Description

 
Pin Symbol Description

1

ISSP SDA

Program Pin Data

2

ISSP SCL

Program Pin Clock

3

SCL

I2C clock line.

4

SDA

I2C data line.

5

/INT

Attention line(Typically active low, optional)

6

RESET

Reset Input. A low on this pin for resets the device.

7

VDD

Power supply.

8

DGND

Ground

6-3) DC Characteristics

 
Item Symbol Min Typ Max Unit

Touch Panel Power supply

VDD

1.71

3.3

3.6

V

6-4) Touch Panel II Specifications

 
Symbol Description Conditions Min. Max. Unit

FSCLI2C

SCL clock frequency

-

0

400

KHz

THDSTAI2C

Hold time (repeated) Start condition.

After this period, the first clock pulse is generated.

-

0.60

-

us

TLOWI2C

LOW period of SCL clock

-

1.3

-

ns

THIGHI2C

HIGH period of SCL clock

-

0.6

-

ns

TSUSTAI2C

Setup time for repeated Start condition

0.6

-

us

THDDATI2C

Data hold time

0

-

us

TSUDATI2C

Data setup time

100

-

ns

TSUSTOI2C

Setup time for STOP condition

0.6

-

us

TBUFI2C

Bus free time between a Stop and Start condition

1.3

-

us

TSPI2C

Pulse width of spikes that are

suppressed by input filter

I2C Specification 3.0 maximum is 50 ns

0

50

ns

CBUS

Capacitance load for SDA or SCL

-

200

[Note6-1]

pF

Figure 6-3. Timing Diagram for Fast/Standard Mode of the I2C Bus

LEGEND

S        I2C Start Condition

Sr        I2C Repeat Start Condition P        I2C Stop Condition

Note6-1 : This does not fully meet the I2C max capacitive load targets of 400 pF.


7-1) AbsoluteMaximumRatings:

 
Parameter Symbol Rating Unit Remark

Logic Supply Voltage

VDD

-0.3 to +7

V

--

Digital voltage supply 2 range

VDD2

-0.6 to+4

V

Note 1

Positive Supply Voltage

VPOS

-0.3 to +18

V

--

Negative Supply Voltage

VNEG

+0.3 to -18

V

--

Max .Drive Voltage Range

VPOS - VNEG

36

V

--

Supply Voltage

VGG

-0.3 to +45

V

--

Supply Voltage

VEE

-25.0 to +0.3

V

--

Supply Range

VGG-VEE

-0.3 to +45

V

--

Operating Temp. Range

TOTR

0 to +50

--

Storage Temperature

TSTG

-25 to +70

--

Note 1: SPI Flash IC Power Supply

7-2) Display Module DC characteristics

 
Parameter Symbol Conditions Min Typ Max Unit

Signal ground

VSS

-

0

-

V

Logic Voltage supply

VDD

3.0

3.3

3.6

V

IVDD

VDD=3.3V

-

1.5

4.0

mA

Logic Voltage supply2 (Active)

VDD2

1.65

1.8

1.95

V

IVDD2

VDD2=1.8V

0.1

0.2

mA

Logic Voltage supply2 (Standby)

VDD2

1.65

1.8

1.95

V

IVDD 2

VDD2=1.8V

25

50

μA

Gate Negative supply

VEE

-21

-20

-19

V

IEE

VEE =-20V

-

1.3

8.0

mA

Gate Positive supply

VGG

21

22

23

V

IGG

VGG = 22V

-

1.4

3.5

mA

Source Negative supply

VNEG

-15.4

-15

-14.6

V

INEG

VNEG = -15V

-

10.4

40

mA

Source Positive supply

VPOS

14.6

15

15.4

V

IPOS

VPOS = 15V

-

10.3

42

mA

Border supply

VBorder

VPOS = 15V

14.6

15

15.4

V

VNEG = -15V

-15.4

-15

-14.6

V

Asymmetry source

VAsym

VPOS+VNEG

-800

0

800

mV

Common voltage

VCOM

-3.5

Adjusted

-1.5

V

ICOM

-

0.3

-

mA

Panel Power

P

-

380

1500

mW

Standby power panel

PSTBY

-

-

0.4

mW

Operating temperature

0

-

50

Storage temperature

-25

-

70

- The maximum power consumption is measured using 85Hz waveform with following pattern transition: from pattern of repeated 1 consecutive black scan lines followed by 1 consecutive white scan line to that of repeated 1 consecutive white scan lines followed by 1 consecutive black scan lines. (Note 7-1)

- The Typical power consumption is measured using 85Hz waveform with following pattern transition: from horizontal 4 gray scale pattern to vertical 4 gray scale pattern. (Note 7-2)

- The standby power is the consumed power when the panel controller is in standby mode.

- The listed electrical/optical characteristics are only guaranteed under the controller & waveform provided by E Ink.

- Vcom is recommended to be set in the range of assigned value ± 0.1V.

- The maximum ICOM inrush current is about 600 mA

Note 7-1

Note 7-2

7-3 ) DisplayModule AC characteristics

VDD=3.0V to 3.6V, unless otherwise specified.

 
Parameter Symbol Min. Typ. Max. Unit

Clock frequency

fckv

-

-

200

kHz

Minimum “L” clock pulse width

twL

0.5

-

-

us

Minimum “H” clock pulse width

twH

0.5

-

-

us

Clock rise time

trckv

-

-

100

ns

Clock fall time

tfckv

-

-

100

ns

SPV setup time

tSU

100

-

twH-100

ns

SPV hold time

tH

100

-

twH-100

ns

Pulse rise time

trspv

-

-

100

ns

Pulse fall time

tfspv

-

-

100

ns

Clock        XCL        cycle time

tcy

25

-

-

ns

D0 .. D7 setup time

tsu

12

-

-

ns

D0 .. D7 hold time

th

12

-

-

ns

XSTL setup time

tstls

12

-

-

ns

XSTL hold time

tstlh

12

-

-

ns

XLE        on        delay time

tLEdly

40

-

-

ns

XLE        high-level pulse width (When VCC=3.0V to 3.6V)

tLEw

150

-

-

ns

XLE        off        delay time

tLEoff

200

-

-

ns

Output setting time to +/- 30mV(Cload=200pF)

tout

-

-

12

us

OUTPUT LATCH CONTROL SIGNALS

CKV & SPV TIMING

GATE OUTPUT TIMING

7-4 ) Controller Timing for WJ-4BIT Waveform

This timing mode is depicted on Figure 1 and Figure 2 and it refers to timing of Source Driver Output Enable (SDOE) and Gate Driver Clock (GDCK). Note, that in this mode LGON follows GDCK timing.

7-5 ) Table Timing Parameters Table

Power Rails must be sequenced in the following order:

1. VSS -7 VDD -7 VNEG -7 VPOS (Source driver) -7 VCOM

2. VSS -7 VDD -7 VEE -7 VGG (Gate driver)

POWER ON

 
  Min Max

Tsd

30us

-

Tdn

100us

-

Tnp

1000us

-

Tpv

100us

-

Tvd

100us

-

Tne

0us

-

Teg

1000us

-

Tgv

100us

-

POWER DOWN

 
  Min Max

Tdv

100μs

-

Tvg

0μs

-

Tgp

0μs

-

Tpn

0μs

-

Tne

0μs

-

Tes

0μs

-

Note9-1:Supply voltages decay through pulldown resistors.

Note9-2:VEE must remain negative of Vcom during decay period.


9-1) Refresh Rate

The module ED060XC3 is applied at a maximum screen refresh rate of 85Hz.

 
  Min Max

Refresh Rate

-

85Hz

10-1) Specifications

Measurements are made by PR650 SepctaScan Colorimeter with that the illumination is at an angle 45° from the perpendicular at the center of sample surface, and the detector is perpendicular unless otherwise specified.


Note : This optical specification is only valid with the integrated touch panel has greater or equal 89% transparency.

 
Symbol Parameter Conditions Min Typ Max Unit Note

R

Reflectance

White

35

40

-

%

Note 10-1

Gn

Nth Grey Level

-

DS+(WS-DS)

×(n-1)/(m-1)

DS+(WS-DS)

×n/(m-1)

DS+(WS-DS)

×(n+1)/(m-1)

L*

-

CR

Contrast Ratio

-

10

12

-

-

WS:White state , DS: Dark state, Gray state from Dark toWhite :DS、G1、G2…、Gn…、Gm-2、WS m:4、8、16 when 2、3、4 bits mode

10-2) Definition of contrast ratio

The contrast ratio (CR) is the ratio between the reflectance in a full white area (Rl) and the reflectance in a dark area (Rd): CR = Rl / Rd

10-3) Reflection Ratio

The reflection ratio is expressed as:


R = Reflectance Factorwhite board x ( Lcenter / Lwhite board ) Lcenter is the luminance measured at center in a white area (R=G=B=1). Lwhite board is the luminance of a standard white board.

E5D

 

00

 

6

 

01

 

1

 

I

 

7

 

4

 

00361

 

A

 

T

1

 

2

 

3

 

4

 

2

 

5

 

6

 

2

 

7

 

2

 

8

1 :EPD model code:

 
EPD model code TFT manufacturer part Number

E5D

E Ink

ED060XC3

E6D

E Ink

ED060XC3P1

E62

CMI

ED060XC3C1

E63

CPT

ED060XC3T1

E6H

Hydis L2

ED060XC3H1

2 :Internal control codes:

3 :FPL reversion code V220:6 V220E:8

4 :FPL batch code:

 

01~99

001~099

G0~G9

160~169

Q0~Q9

230~239

X0~X9

300~309

A0~A9

100~109

H0~H9

170~179

R0~R9

240~249

Y0~Y9

310~319

B0~B9

110~119

J0~J9

180~189

S0~S9

250~259

Z0~Z9

320~329

C0~C9

120~129

K0~K9

190~199

T0~T9

260~269

 

D0~D9

130~139

L0~L9

200~209

U0~U9

270~279

E0~E9

140~149

M0~M9

210~219

V0~V9

280~289

F0~F9

150~159

N0~N9

220~229

W0~W9

290~299

5 :Year:

F: 2005 / G: 2006 / H: 2007 / I: 2008 /... / Z: 2024

6 :Month:

1:Jan. 2:Feb. ... 9:Sep. A:Oct. B:Nov. C:Dec.

7 :Serial number

00000-99999

8: MFG code:

 
Module Manufacturer Code Translation

T

TOC FAB3

Y

TOC FAB2

K

TOC FAB1

P

EIH

S

MOS

V

Microview

G

TYT FAB5

L

TYT FAB4

 

Product Number

EPD

Model

TFT

FPL

Version

FPL

Batch

Module Manufacturer

Remark

ED060XC3C1

E62

CMI

6

013

K,T,Y,S

available for MP and engineering samples

ED060XC3C1

E62

CMI

6

013

P

available for engineering samples

ED060XC3P1

E6D

E Ink

6

001

K,T,Y,S

available for MP and engineering samples

ED060XC3P1

E6D

E Ink

6

001

P

available for engineering samples

ED060XC3T1

E63

CPT

6

013

K,T,Y,S

available for MP and engineering samples

ED060XC3T1

E63

CPT

6

013

P

available for engineering samples

ED060XC3H1

E6H

Hydis

6

001

K,T,Y,S

available for MP and engineering samples

ED060XC3H1

E6H

Hydis

6

001

P

available for engineering samples

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